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CY23FP12-002
200-MHz Field Programmable Zero Delay Buffer
Features
* Pre-programmed Configurations * Fully field-programmable -- Input and output dividers -- Inverting/noninverting outputs -- Phase-locked loop (PLL) or fanout buffer configuration 10-MHz to 200-MHz operating range Split 2.5V or 3.3V outputs Two LVCMOS reference inputs Twelve low-skew outputs -- Output-output skew < 200 ps -- Device-device skew < 500 ps Input-output skew < 250 ps Cycle-cycle jitter < 100 ps (typical) Three-stateable outputs < 50-A shutdown current Spread Aware 28-pin SSOP 3.3V operation Industrial temperature available
Functional Description
The CY23FP12-002 is a pre-programmed version of the CY23FP12. It features a high-performance fully field-programmable 200 MHz zero delay buffer designed for high speed clock distribution. The integrated PLL is designed for low jitter and optimized for noise rejection. These parameters are critical for reference clock distribution in systems using highperformance ASICs and microprocessors. The CY23FP12-002 is fully programmable via volume or prototype programmers enabling the user to define an application-specific Zero Delay Buffer with customized input and output dividers, feedback topology (internal/external), output inversions, and output drive strengths. For additional flexibility, the user can mix and match multiple functions, listed in Table 2, and assign a particular function set to any one of the four possible S1-S2 control bit combinations. This feature allows for the implementation of four distinct personalities, selectable with S1-S2 bits, on a single programmed silicon. The CY23FP12-002 also features a proprietary auto-powerdown circuit that shuts down the device in case of a REF failure, resulting in less than 50 A of current draw. The CY23FP12-002 provides twelve outputs grouped in two banks with separate power supply pins which can be connected independently to either a 2.5V or a 3.3V rail. Selectable reference input is a fault tolerance feature which allows for glitch-free switch over to secondary clock source when REFSEL is asserted/de-asserted.
* * * *
* * * * * * * *
Block Diagram
VDDC VDDA CLKA0
Lock Detect
Pin Configuration
SSOP Top View
REF2 REF1 CLKB0 CLKB1 VSSB CLKB2 CLKB3 VDDB VSSB CLKB4 CLKB5 VDDB VDDC S2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
CLKA1 CLKA2 CLKA3
REFSEL FBK CLKA0 CLKA1 VSSA CLKA2 CLKA3 VDDA VSSA CLKA4 CLKA5 VDDA VSSC S1
REFSEL
REF1 REF2 FBK
/M /N 100 to 400MHz PLL /1 /2 /3 /4 /X /2X
CLKA4 CLKA5 VSSA VDDB CLKB0 CLKB1 CLKB2 CLKB3
Test Logic
S[2:1] VSSC
Function Selection
CLKB4 CLKB5 VSSB
Cypress Semiconductor Corporation Document #: 38-07644 Rev. **
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised February 25, 2004
CY23FP12-002
Pin Description
.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Name REF2 REF1 CLKB0 CLKB1 VSSB CLKB2 CLKB3 VDDB VSSB CLKB4 CLKB5 VDDB VDDC S2 S1 VSSC VDDA CLKA5 CLKA4 VSSA VDDA CLKA3 CLKA2 VSSA CLKA1 CLKA0 FBK REFSEL I I O O PWR O O PWR PWR O O PWR PWR I I PWR PWR O O PWR PWR O O PWR O O I I
I/O
Type LVTTL/LVCMOS LVTTL/LVCMOS LVTTL LVTTL POWER LVTTL LVTTL POWER POWER LVTTL LVTTL POWER POWER LVTTL LVTTL POWER POWER LVTTL LVTTL POWER POWER LVTTL LVTTL POWER LVTTL LVTTL LVTTL LVTTL
Description Input reference frequency, 5V-tolerant input. Input reference frequency, 5V-tolerant input. Clock output, Bank B. Clock output, Bank B. Ground for Bank B. Clock output, Bank B. Clock output, Bank B. 2.5V or 3.3V supply, Bank B. Ground for Bank B. Clock output, Bank B. Clock output, Bank B. 2.5V or 3.3V supply, Bank B. 3.3V core supply. Select input. Select input. Ground for core. 2.5V or 3.3V supply, Bank A. Clock output, Bank A. Clock output, Bank A. Ground for Bank A. 2.5V or 3.3V supply Bank A. Clock output, Bank A. Clock output, Bank A. Ground for Bank A. Clock output, Bank A. CLock output, Bank A. PLL feedback input. Reference select input. REFSEL = 0, REF1 is selected. REFSEL = 1, REF2 is selected.
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CY23FP12-002
/1,/2,/3,/4, /x,/2x
CLKB5 CLKB4
/1,/2,/3,/4, /x,/2x
CLKB3 CLKB2
REF
/M PLL
/1,/2,/3,/4, /x,/2x
Output Function Select Matrix
CLKB1 CLKB0
FBK
/N
/1,/2,/3,/4, /x,/2x
CLKA5 CLKA4
/1,/2,/3,/4, /x,/2x
CLKA3 CLKA2
/1,/2,/3,/4, /x,/2x
CLKA1 CLKA0
Figure 1. Basic PLL Block Diagram Below is a list of independent functions that can be programmed with a volume or prototype programmer on the "pre-programmed" silicon. Table 1. Configuration DC Drive Bank A Description Default Programs the drive strength of Bank A outputs. The user can select one out +20 mA of two possible drive strength settings that produce output DC currents in the range of 16 mA to 20 mA. Programs the drive strength of Bank B outputs. The user can select one out +20 mA of two possible drive strength settings that produce output DC currents in the range of 16 mA to 20 mA. Enables/Disables CLKB[5:0] outputs. Each of the six outputs can be disabled Enable individually if not used, to minimize electromagnetic interference (EMI) and switching noise. Enables/Disables CLKA[5:0] outputs. Each of the six outputs can be disabled Enable individually if not used, to minimize EMI and switching noise. Generates an inverted clock on the CLKA0 output. When this option is programmed, CLKA0 and CLKA1 will become complimentary pairs. Generates an inverted clock on the CLKA2 output. When this option is programmed, CLKA2 and CLKA3 will become complimentary pairs. Generates an inverted clock on the CLKA4 output. When this option is programmed, CLKA4 and CLKA5 will become complimentary pairs. Generates an inverted clock on the CLKB0 output. When this option is programmed, CLKB0 and CLKB1 will become complimentary pairs. Generates an inverted clock on the CLKB2 output. When this option is programmed, CLKB2 and CLKB3 will become complimentary pairs. Non-invert Non-invert Non-invert Non-invert Non-invert
DC Drive Bank B
Output Enable for Bank B clocks
Output Enable for Bank A clocks Inv CLKA0 Inv CLKA2 Inv CLKA4 Inv CLKB0 Inv CLKB2
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CY23FP12-002
Table 1. (continued) Configuration Inv CLKB4 Pull-down Enable Fbk Pull-down Enable Fbk Sel Description Generates an inverted clock on the CLKB4 output. When this option is programmed, CLKB4 and CLKB5 will become complimentary pairs. Enables/Disables internal pulldowns on all outputs Default Non-invert Enable
Enables/Disables internal pulldowns on the feedback path (applicable to both Enable internal and external feedback topologies) Selects between the internal and the external feedback topologies Internal
Below is a list of independent functions, which can be assigned to each of the four S1 and S2 combinations. When a particular S1 and S2 combination is selected, the device will assume the configuration (which is essentially a set of functions given in Table 2, below) that has been preassigned to that particular combination. Table 2. Function Description Default Enable Enable Enable Enable Enable Enable Output Enable CLKB[5:4] Enables/Disables CLKB[5:4] output pair Output Enable CLKB[3:2] Enables/Disables CLKB[3:2] output pair Output Enable CLKB[1:0] Enables/Disables CLKB[1:0] output pair Output Enable CLKA[5:4] Enables/Disables CLKA[5:4] output pair Output Enable CLKA[3:2] Enables/Disables CLKA[3:2] output pair Output Enable CLKA[1:0] Enables/Disables CLKA[1:0] output pair
Auto Power-down Enable Enables/Disables the auto power down circuit, which monitors the reference clock rising Enable edges and shuts down the device in case of a reference "failure." This failure is triggered by a drift in reference frequency below a set limit. This auto power down circuit is disabled internally when one or more of the outputs are configured to be driven directly from the reference clock. PLL Power-down M[7:0] N[7:0] X[6:0] Shuts down the PLL when the device is configured as a non-PLL fanout buffer. See Table 4
Assigns an eight-bit value to reference divider -M. The divider can be any integer value See from 1 to 256; however, the PLL input frequency cannot be lower than 10 MHz. Table 4 Assigns an eight-bit value to feedback divider -N. The divider can be any integer value See from 1 to 256; however, the PLL input frequency cannot be lower than 10 MHz. Table 4 Assigns a seven-bit value to output divider -X. The divider can be any integer value from 5 to 130. Divide by 1,2,3, and 4 are preprogrammed on the device and can be activated by the appropriate output mux setting. Selects between the PLL output and the reference clock as the source clock for the output dividers. See Table 4 See Table 4
Divider Source CLKA54 Source CLKA32 Source CLKA10 Source CLKB54 Source CLKB32 Source CLKB10 Source
Independently selects one out of the eight possible output dividers that will connect to See the CLKA5 and CLKA4 pair. Please refer to Table 3 for a list of divider values. Table 4 Independently selects one out of the eight possible output dividers that will connect to See the CLKA3 and CLKA2 pair. Please refer to Table 3 for a list of divider values. Table 4 Independently selects one out of the eight possible output dividers that will connect to See the CLKA1 and CLKA0 pair. Please refer to Table 3 for a list of divider values. Table 4 Independently selects one out of the eight possible output dividers that will connect to See the CLKB5 and CLKB4 pair. Please refer to Table 3 for a list of divider values. Table 4 Independently selects one out of the eight possible output dividers that will connect to See the CLKB3 and CLKB2 pair. Please refer to Table 3 for a list of divider values. Table 4 Independently selects one out of the eight possible output dividers that will connect to See the CLKB1 and CLKB0 pair. Please refer to Table 3 for a list of divider values. Table 4
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CY23FP12-002
Table 3 is a list of output dividers that are independently selected to connect to each output pair. In the default (pre-programmed) state of the device, S1 and S2 pins will function, as indicated in Table 4. One possible example output is shown in this table. This example is for illustration purposes only, since many other frequency combinations are possible for each pre-programmed configuration. Table 3. CLKA/B Source 0 [000] 1 [001] 2 [010] 3 [011] 4 [100] 5 [101] 6 [110] Output Connects To REF Divide by 1 Divide by 2 Divide by 3 Divide by 4 Divide by X Divide by 2X[1] Field Programming the CY23FP12-002 The CY23FP12-002 is programmed at the package level, i.e. in a programmer socket. The CY23FP12-002 is flashtechnology based, so the parts can be reprogrammed up to 100 times. This allows for fast and easy design changes and product updates, and eliminates any issues with old and outof-date inventory. Samples and small prototype quantities can be programmed on the CY3672 programmer. Cypress's value-added distribution partners and third-party programming systems from BP Microsystems, HiLo Systems, and others are available for large production quantities. CyberClocks Software CyberClocks is an easy-to-use software application that allows the user to custom-configure the CY23FP12-002. Users can specify the REF, PLL frequency, output frequencies and/or post-dividers, and different functional options. CyberClocks outputs an industry standard JEDEC file used for programming the CY23FP12-002. CyberClocks can be downloaded free of charge from the Cypress website at www.cypress.com. CY3672 FTG Development Kit The Cypress CY3672 FTG Development Kit comes complete with everything needed to design with the CY23FP12-002 and program samples and small prototype quantities. The kit comes with the latest version of CyberClocks and a small portable programmer that connects to a PC serial port for on-the-fly programming of custom frequencies. The JEDEC file output of CyberClocks can be downloaded to the portable programmer for small-volume programming, or for use with a production programming system for larger volumes.
7 [111] TEST mode [LOCK signal][2] Table 4. Pre-Programmed Configuration Example Output Outputs S2, S1 DivSrc ClkA0, A1 ClkA2, A3 ClkA4, A5 ClkB0, B1 ClkB2, B3 ClkB4, B5 ClkA0, A1 ClkA2, A3 ClkA4, A5 ClkB0, B1 ClkB2, B3 ClkB4, B5 ClkA0, A1 ClkA2, A3 ClkA4, A5 ClkB0, B1 ClkB2, B3 ClkB4, B5 ClkA0, A1 ClkA2, A3 ClkA4, A5 ClkB0, B1 ClkB2, B3 ClkB4, B5 00 00 00 00 00 00 01 01 01 01 01 01 10 10 10 10 10 10 11 11 11 11 11 11 1 3 X=6 X=6 4 Ref 4 4 4 4 X=8 X=8 X=8 X=8 X=8 4 4 4 Ref Ref Ref 2 2 2 REF Input Output (MHz) VCO (MHz) (MHz) 25 25 25 25 25 25 100 100 100 100 100 100 33.3 33.3 33.3 33.3 33.3 33.3 100 100 100 100 100 100 200 200 200 200 200 200 200 200 200 200 200 200 266.6 266.6 266.6 266.6 266.6 266.6 powerdown powerdown powerdown powerdown powerdown powerdown 200 66.7 33.3 33.3 50 25 50 50 50 50 25 25 33.3 33.3 33.3 66.6 66.6 66.6 100 100 100 50 50 50
CY23FP12-002 Frequency Calculation
The CY23FP12-002 is an extremely flexible clock buffer with up to twelve individual outputs, generated from an integrated PLL. There are four variables used to determine the final output frequency. These are the input Reference Frequency M, the N dividers, and the post divider X. The basic PLL block diagram is shown in Figure 1. Each of the six clock outputs pair has many output options available to it. There are six post divider options: /1, /2, /3, /4, /X, and /2X. The post divider options can be applied to the calculated PLL frequency or to the REF directly. The feedback either is connected to CLKA0 internally or connected to any output externally. A programmable divider, M, is inserted between the reference input, REF, and the phase detector. The divider M can be any integer 1 to 256. The PLL input frequency cannot be lower than 10 MHz or higher than 200 MHz. A programmable divider, N, is inserted between the feedback input, FBK, and the phase detector. The divider N can be any integer 1 to 256. The PLL input frequency cannot be lower than 10 MHz or higher than 200 MHz. So the output can be calculated as following: FREF / M = FFBK / N. FPLL = (FREF * N * post divider)/M. FOUT = FPLL / post divider. In addition to above divider options, the another option bypasses the PLL and passes the REF directly to the output. FOUT = FREF.
Note: 1. Outputs will be rising edge aligned only to those outputs using this same device setting. 2. When the source of an output pair is set to [111], the output pair becomes lock indicator signal. For example, if the source of an output pair (CLKA0, CLKA1) is set to [111], the CLKA0 and CLKA1, becomes lock indicator signals. In non-invert mode, CLKA0 and CLKA1 signals will be high when the PLL is in lock mode. If CLKA0 is in an invert mode, the CLKA0 will be low and the CLKA1 will be high when the PLL is in lock mode.
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CY23FP12-002
Absolute Maximum Conditions
Parameter VDD VIN VIN LUI TS TA TA TJ OJc OJa ESDh MSL GATES UL-94 FIT TPU Description Supply Voltage Input Voltage REF Input Voltage Except REF Latch-up Immunity Temperature, Storage Temperature, Operating Ambient Temperature, Operating Ambient Junction Temperature Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Moisture Sensitivity Level Total Functional Gate Count Flammability Rating Failure in Time Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Assembled Die @ 1/8 in. Manufacturing test 0.05 Condition Non-functional Relative to VCC Relative to VCC Functional Non-functional Commercial Temperature Industrial Temperature Industrial Temperature Functional Functional 34 86 2000 MSL - 1 21375 V-0 10 500 -65 0 -40 Min. -0.5 -0.5 -0.5 300 +125 +70 +85 125 Max. 7 7 VDD + 0.5 Unit VDC VDC VDC mA C C C C C/W C/W V class each class ppm ms
DC Electrical Specifications for CY23FP12-002SC/I
Parameter VDDC VDDA, VDDB VIL VIH IIL IIH VOL VOH IDDS IDD Description Core Supply Voltage Bank A, Bank B Supply Voltage Input LOW Input LOW Voltage[3] 0.7 x VDD VIN = 0V VDDA/VDDB = 3.3V, IOL = 16 mA (standard drive) VDDA/VDDB = 3.3V, IOL = 20 mA (high drive) VDDA/VDDB = 2.5V, IOL = 16 mA (high drive) VDDA/VDDB = 3.3V, IOH = -16 mA (standard drive) VDDA/VDDB = 3.3V, IOH = -20 mA (high drive) VDDA/VDDB = 2.5V, IOH = -16 mA (high drive) REF = 0 MHz VDDA = VDDB = 2.5V, Unloaded outputs @ 166 MHz VDDA = VDDB = 2.5V, Loaded outputs @ 166 MHz, CL = 15 pF VDDA = VDDB = 3.3V, Unloaded outputs @ 166 MHz VDDA = VDDB = 3.3V, Loaded outputs @ 166 MHz, CL = 15 pF
Notes: 3. Applies to both Ref Clock and FBK. 4. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Test Conditions
Min. 3.135 3.135 2.375
Typ.
Max. 3.465 3.465 2.625 0.3 x VDD 50.0 50.0 0.5
Unit V V V V V A A V
Input HIGH Voltage[3] Current[3] Input HIGH Current[3] VIN = VDD Output LOW Voltage[4]
Output HIGH Voltage[4] Power-down Supply Current Supply Current
VDD - 0.5 12 40 65 50 100 50 65.0 100 80 120
V
A mA
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CY23FP12-002
Switching Characteristics for CY23FP12-002SC/I [5]
Parameter Description Reference Frequency[6] Reference Edge Rate Reference Duty Cycle t1 Output Frequency[7] CL = 15 pF, Commercial Temperature CL = 15 pF, Industrial Temperature CL = 30 pF, Commercial Temperature CL = 30 pF, Industrial Temperature Duty Cycle[5] t3 Rise Time[5] VDDA/B = 3.3V, measured at VDD/2 VDDA/B = 2.5V VDDA/B = 3.3V, 0.8V to 2.0V, CL = 30 pF (standard drive and high drive) VDDA/B = 3.3V, 0.8V to 2.0V, CL = 15 pF (standard drive and high drive) VDDA/B = 2.5V, 0.6V to 1.8V, CL = 30 pF (high drive only) VDDA/B = 2.5V, 0.6V to 1.8V, CL = 15 pF (high drive only) t4 Fall Time[5] VDDA/B = 3.3V, 0.8V to 2.0V, CL = 30 pF (standard drive and high drive) VDDA/B = 3.3V, 0.8V to 2.0V, CL = 15 pF (standard drive and high drive) VDDA/B = 2.5V, 0.6V to 1.8V, CL = 30 pF (high drive only) VDDA/B = 2.5V, 0.6V to 1.8V, CL = 15 pF (high drive only) TTB Total Timing Budget,[8,9] Bank A and B same frequency Total Timing Budget, Bank A and B different frequency t5 Output to Output Skew[5] Bank to Bank Skew Bank to Bank Skew Bank to Bank Skew t6 t7 tJ All outputs equally loaded Same frequency Different frequency Different voltage, same frequency 0 0 Outputs @200 MHz, tracking skew not included Test Conditions Min. 10 1 25 10 10 10 10 45.0 40.0 50.0 50.0 75 200 166.7 100 83.3 55.0 60.0 1.6 0.8 2.0 1.0 1.6 0.8 1.6 0.8 650 ps ns ns % Typ. Max. 200 Unit MHz V/ns % MHz
850 200 200 400 400 250 500 200 400 ps ps ps ps
Input to Output Skew (static Measured at VDD/2, REF to FBK phase offset)[5] Device to Device Skew[5] Cycle to Cycle Jitter[5] (Peak-to-peak) Cycle to Cycle Jitter[5] (Peak-to-peak) Measured at VDD/2 Bank A and B same frequency Bank A and B different frequency
Notes: 5. All parameters are specified with loaded outputs. 6. When the device is configured as a non-PLL fanout buffer (PLL Power-down enabled), the reference frequency can be lower than 10MHz. With auto powerdown disabled and PLL power-down enabled, the reference frequency can be as low as DC level. 7. When the device is configured as a non-PLL fanout buffer (PLL Power-down enabled), the output frequency can be lower than 10MHz. With auto power-down disabled and PLL power-down enabled, the output frequency can be as low as DC level. 8. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. 9. TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply voltage, operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output skew, cycle-cycle jitter, and dynamic phase error.TTB will be equal to or smaller than the maximum specified value at a given frequency.
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CY23FP12-002
Switching Characteristics for CY23FP12-002SC/I [5]
Parameter ttsk tLOCK TLD Description Tracking Skew PLL Lock Time[5] Inserted Loop Delay Test Conditions Input reference clock @ < 50-KHz modulation with 3.75% spread Stable power supply, valid clock at REF Max loop delay for PLL Lock (stable frequency) Max loop delay to meet Tracking Skew Spec Min. Typ. Max. 200 1.0 7 4 Unit ps ms ns ns
Switching Waveforms
Duty Cycle Timing
t1 t2 1.4V 1.4V 1.4V
All Outputs Rise/Fall Time
OUTPUT 2.0V 0.8V t3 2.0V 0.8V t4 3.3V 0V
Output-Output Skew
OUTPUT 1.4V
OUTPUT t5
1.4V
Input-Output Propagation Delay
INPUT VDD/2
FBK t6
VDD/2
Device-Device Skew
FBK, Device 1 VDD/2
FBK, Device 2 t7
VDD/2
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CY23FP12-002
Test Circuits
Test Circuit # 1 VDD 0.1 F OUTPUTS V DD 0.1 F GND GND CLK OUT C LOAD
Test Circuit for all parameters
Ordering Information
Ordering Code CY23FP12OC-002 CY23FP12OC-002T CY23FP12OI-002 CY23FP12OI-002T CY3672 CY3692 Package Type 28-pin SSOP 28-pin SSOP - Tape and Reel 28-pin SSOP 28-pin SSOP - Tape and Reel Development Kit CY23FP12S Socket (Label CY3672 ADP006) Operating Range Commercial, 0C to 70C Commercial,0C to 70C Industrial, -40C to 85C Industrial, -40C to 85C
Package Drawing and Dimension
28-lead (5.3 mm) Shrunk Small Outline Package O28
51-85079-*C
Total Timing Budget, TTB, Spread Aware, and CyberClocks are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY23FP12-002
Document History Page
Document Title: CY23FP12-002 200-MHz Field Programmable Zero Delay Buffer Document Number: 38-07644 REV. ** ECN NO. 206761 Issue Date See ECN Orig. of Change RGL New Data Sheet Description of Change
Document #: 38-07644 Rev. **
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